1. Field of the Invention
The present invention relates to a method of manufacturing semiconductor integrated circuits. More particularly, the present invention relates to a method of manufacturing a high aspect ratio shallow trench isolation region.
2. Description of the Related Arts
Recently, as the manufacturing techniques of semiconductor integrated circuits develop, the number of elements in a chip increases. The size of the element decreases as the degree of integration increases. The line width used in manufacturing lines has decreased from sub-micron to quarter-micron, or even smaller. However, regardless of the reduction of the size of the element, adequate insulation or isolation must be formed among individual elements in the chip so that good element characteristics can be achieved. This technique is called device isolation technology. The main object is to form an isolation region, and reduce the size of the isolation as much as possible while assuring good isolation to have more chip space for more elements.
Among different element isolation techniques, LOCOS and shallow trench isolation region manufacturing methods are the most commonly used. In particular, as the latter has a small isolation region and can keep the substrate level after the process is finished, it is the semiconductor manufacturing method receiving the most attention. The conventional manufacturing method for a shallow trench isolation region comprises forming a dielectric layer to fill a trench on a substrate by chemical vapor deposition (CVD), and etching back the dielectric layer on the substrate to remove the redundant dielectric layer. However, as the density of the semiconductor integrated circuits increases and the size of the elements decreases, the above mentioned deposition have problems in step coverage and cannot completely fill the trench. This influences the isolation effect among elements.
High density plasma chemical vapor deposition (HDPCVD) has extremely good gap-filling ability and is suitable for fine shallow trench isolation region manufacturing. However, the oxide layer deposited by HDPCVD has a distinctive topography which has to be leveled by chemical mechanical polishing (CMP).
At present, the manufacturing method of a shallow trench isolation region usually utilizes HDPCVD for better step coverage in the trench. To further illustrate the process, the manufacturing method is shown in cross section in FIGS. 1A to 1B.
As shown in FIG. 1A, a shield layer is formed on a substrate 10, for example, a pad oxide layer 11 with a thickness of 50 Å to 200 Å is formed on a silicon substrate 10 by CVD or thermal oxidation, and a silicon nitride layer 12 with a thickness of 1200 Å to 1700 Å is deposited on the pad oxide layer 11 by the CVD. The pad oxide layer 11 and the silicon nitride layer 12 form a shield layer. Next, a photoresist layer is coated on the silicon nitride layer 12 and is patterned using photolithography to expose the portion where the element isolation region is to be formed. The silicon nitride layer 12 and the pad oxide layer 11 are etched sequentially using the photoresist layer as a mask. After the photoresist layer is removed with adequate liquid, the silicon nitride layer 12 and the pad oxide layer 11 are used as a mask to etch silicon substrate 10, and a trench with a thickness of 5000 Å to 6000 Å is formed for the isolation of elements.
Next, as shown in FIG. 1B, thermal oxidation is performed to grow a thin oxide layer 14 with a thickness of 180 Å˜220 Å as a liner covering the bottom and sidewall of the trench. After that, HDPCVD is performed, for example using O2 and SiH4 as reactants with Ar or O2 or He sputtering to deposit a silicon dioxide layer 18 as an insulation layer, and the trench is filled as shown in FIG. 1B. The silicon dioxide layer 18 has an undulate surface due to the different density of the trench distribution and the characteristics of HDPCVD.
The manufacturing method of a high aspect ratio shallow trench isolation region presently has the drawback as shown in FIGS. 1C and 1D.
As shown in FIG. 1C, as the opening width of the trench narrows and/or the aspect ratio of the trench increases, for example the opening width is less than 0.15 μm and/or the aspect ratio is larger than 3, the silicon dioxide layer 18 deposited using HDPCVD at present may have voids which result in poor insulation quality of the shallow trench isolation region.
In addition, as shown in FIG. 1D, debris 21 produced during Ar or O2 or He sputtering in HDPCVD may remain inside the trench, and this results in void formation.